DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 767

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Instances in Multiple Transceiver Blocks
Combining Transceiver Instances in Multiple Transceiver Blocks
February 2011 Altera Corporation
Figure 3–4
Figure 3–4. Combined Transceiver Instances After Compilation for Example 3
The method to instantiate multiple transceiver channels using a single ALTGX
instance is described in
following section describes the method to instantiate multiple transceiver channels
using multiple transceiver blocks.
When you create a transceiver instance that has more than four transceiver channels
(assuming that the instance is created in non-Basic (PMA Direct) functional mode
which requires regular channels), the Quartus II software attempts to combine the
transceiver channels in multiple transceiver blocks. This is shown in the following
examples.
shows the transceiver channel instances after compilation.
“Creating Transceiver Channel Instances” on page
Inst 2
Effective Data Rate: 1.25 Gbps
Inst 3
Effective Data Rate: 2 Gbps
Inst 0
Effective Data Rate: 3.25 Gbps
Inst 1
Effective Data Rate: 2.5 Gbps
Transceiver Channel1
Transceiver Channel0
TX Loc Div: /1
TX Loc Div: /1
Transceiver Block
TX Channel
RX Channel
Base Data Rate:
Base Data Rate:
RX Channel
TX Channel
3.125 Gbps
1.25 Gbps
CMU PLL
CMU PLL
Stratix IV Device Handbook Volume 2: Transceivers
3–3. The
3–13