DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 840

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

4–34
Figure 4–19. Reset Sequence with CDR in Manual Lock Mode
Notes to
(1) For t
(2) For t
(3) For t
Stratix IV Device Handbook Volume 2: Transceivers
Figure 4–19
pll_powerdown
LTR_LTD_Manual
LTD_Manual
duration, refer to the
Reset and Power Down Signals
duration, refer to the
duration, refer to the
Receiver and Transmitter Channel Set-up—Receiver CDR in Manual Lock
Mode
This configuration contains both a transmitter and receiver channel. For Basic (PMA
Direct) drive ×1 mode, with receiver CDR in manual lock mode, use the reset
sequence shown in
mode.
Ouput Status Signals
CDR Control Signals
pll_powerdown[0]
pll_powerdown[3]
rx_analogreset[0]
rx_analogreset[3]
rx_locktorefclk[0]
rx_locktorefclk[3]
rx_dataout[63:0]
rx_locktodata[0]
rx_pll_locked[0]
rx_locktodata[3]
rx_pll_locked[3]
pll_locked
DC and Switching Characteristics for Stratix IV Devices
busy
DC and Switching Characteristics for Stratix IV Devices
DC and Switching Characteristics for Stratix IV Devices
1
t
pll_powerdown (1)
Figure
2
3
4–19. In this example, four channels are configured in this
Minimum of Two Parallel Clock Cycles
4
5
5
t
6
6
LTR_LTD_Manual (2)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
7
7
7
7
t
LTD_Manual (3)
chapter.
chapter.
chapter.
8
valid parallel data into FPGA fabric
PMA Direct Drive Mode Reset Sequences
February 2011 Altera Corporation