DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 698

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–26
Table 2–6. Transmitter Channel Datapath Clock Frequencies in Non-Bonded Functional Modes
Stratix IV Device Handbook Volume 2: Transceivers
PCIe ×1 (Gen 1)
PCIe ×1 (Gen 2)
GIGE
Serial RapidIO
SONET/SDH OC12
SONET/SDH OC48
HD-SDI
3G-SDI
Functional Mode
f
1
In non-bonded channel configurations clocked by the CMU PLL, each channel can
derive its clock independently from either CMU0 PLL or CMU1 PLL within the same
transceiver block. The CMU PLL synthesizes the input reference clock to generate a
clock that is distributed to the local clock divider block in each channel using the ×1
high-speed serial clock line. Depending on the configured functional mode, the local
clock divider block in each channel generates the low-speed parallel clock and
high-speed serial clock. The serializer in the transmitter channel PMA uses both the
low-speed parallel clock and high-speed serial clock for its parallel-in-serial-out
operation. The low-speed parallel clock clocks the 8B/10B encoder (if enabled) and
the write port of the byte serializer (if enabled) in the transmitter channel PCS.
Depending on whether you use the byte serializer or not, the low-speed parallel clock
(when you do not use the byte serializer) or a divide-by-two version of the low-speed
parallel clock (when you use the byte serializer) from the CMU0 clock divider block
clocks the read port of the transmitter phase compensation FIFO in all four bonded
channels. This clock is driven directly on the tx_clkout port as the FPGA
fabric-Transceiver interface clock. You can use the coreclkout signal to clock the
transmitter data and control logic in the FPGA fabric for all four bonded channels.
If you configure the ATX PLL to clock the transmitter channel, the ATX PLL block
drives the high-speed serial clock and low-speed parallel clock to the transmitter
channel on the ×N_Top or ×N_Bottom lines.
For more information, refer to the
Stratix IV Devices
Table 2–2
functional modes that have a fixed data rate.
1.4835 Gbps
3.125 Gbps
2.488 Gbps
1.485 Gbps
2.967 Gbps
Data Rate
1.25 Gbps
1.25 Gbps
622 Mbps
2.97 Gbps
2.5 Gbps
2.5 Gbps
5 Gbps
lists the transmitter channel datapath clock frequencies in non-bonded
chapter.
High-Speed Serial
Clock Frequency
741.75 MHz
1.5625 GHz
1.4835 GHz
742.5 MHz
1.244 GHz
1.485 GHz
1.25 GHz
625 MHz
625 MHz
1.25 GHz
311 MHz
2.5 GHz
Configuring Multiple Protocols and Data Rates in
Frequency (MHz)
Parallel Clock
Low-Speed
148.35
312.5
77.75
148.5
296.7
250
500
125
125
250
311
297
Chapter 2: Transceiver Clocking in Stratix IV Devices
Without Byte
Transceiver Channel Datapath Clocking
Interface Clock Frequency
Serializer
FPGA Fabric-Transceiver
148.35
(MHz)
77.75
148.5
February 2011 Altera Corporation
250
125
N/A
N/A
N/A
N/A
N/A
N/A
N/A
With Byte
Serializer
156.25
74.175
148.35
(MHz)
155.5
74.25
148.5
62.5
125
250
125
N/A
N/A