DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 117
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 117 of 1154
- Download datasheet (32Mb)
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
SIV51005-3.2
Clock Networks in Stratix IV Devices
Table 5–1. Clock Resources in Stratix IV Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 1
February 2011
February 2011
February 2011
SIV51005-3.2
SIV51005-3.2
Clock input pins
GCLK networks
RCLK networks
PCLK networks
GCLKs/RCLKs per
quadrant
Clock Resource
This chapter describes the hierarchical clock networks and phase-locked loops (PLLs)
which have advanced features in Stratix
ability to reconfigure the PLL counter clock frequency and phase shift in real time,
allowing you to sweep PLL output frequencies and dynamically adjust the output
clock phase shift.
The Quartus
devices. The following sections describe the Stratix IV clock networks and PLLs in
detail:
■
■
The global clock networks (GCLKs), regional clock networks (RCLKs), and periphery
clock networks (PCLKs) available in Stratix IV devices are organized into hierarchical
clock structures that provide up to 236 unique clock domains (16 GCLKs + 88 RCLKs
+ 132 PCLKs) within the Stratix IV device and allow up to 71 unique GCLK, RCLK,
and PCLK clock sources (16 GCLKs + 22 RCLKs + 33 PCLKs) per device quadrant.
Table 5–1
Number of Resources Available
56/88/112/132 (33 per device
“Clock Networks in Stratix IV Devices” on page 5–1
“PLLs in Stratix IV Devices” on page 5–19
32 Single-ended
(16 Differential)
quadrant)
lists the clock resources available in Stratix IV devices.
64/88
32/38
®
II software enables the PLLs and their features without external
16
(1)
(3)
(2)
5. Clock Networks and PLLs in Stratix IV
DPA clock outputs, PLD-transceiver interface clocks, horizontal
CLK[0..15]p and CLK[0..15]n pins, PLL clock outputs, and
CLK[0..15]p and CLK[0..15]n pins, PLL clock outputs, and
®
IV devices. It includes details about the
CLK[0..15]p and CLK[0..15]n pins
Source of Clock Resource
I/O pins, and logic array
16 GCLKs + 16 RCLKs
16 GCLKs + 22 RCLKs
logic array
logic array
Devices
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