DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 795

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Combining Transceiver Channels in Basic (PMA Direct) Configurations
February 2011 Altera Corporation
You can also combine channels configured in Basic (PMA Direct) ×N mode with
bonded ×4 and ×8 functional modes. For example scenarios, refer to
page 3–19
Consider the unsupported placement design example shown
placement is unsupported because of the ×N_Top clock line contention between the
ATX PLL and the CMU0 PLL in transceiver block 0.
Figure 3–22. Unsupported Placement Due to ×N Clock Line Contention for Example 11
Note to
(1) The red lines represent the ×N top clock line and the blue lines represent the ×4 clock line.
Example 11
Figure
and
3–22:
Figure 3–10 on page
CMU0
PLL
CMU0 Channel
Inst0:Channel 0
Inst0:Channel 1
Inst0:Channel 2
Inst0:Channel 3
Inst0:Channel 4
Inst0:Channel 5
Inst0:Channel 6
Inst0:Channel 7
Inst0:Channel 8
Inst0:Channel 9
Inst1:Channel 0
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
Inst0:Channel 1
Inst0:Channel 1
ATX PLL R1
GXBR1
(5 Gbps)
GXBR0
Central
TX
TX
TX
TX
TX
Divider
TX
TX
TX
TX
TX
TX
Clock
3–22.
using the clock
Contention in
This channel cannot get its clock from the
line
ATX PLL due to clock contention
x4 Clock Line (1)
Stratix IV Device Handbook Volume 2: Transceivers
xN Top Clock Line (1)
Figure
Figure 3–8 on
3–22. The
3–41