DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 780

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

3–26
Stratix IV Device Handbook Volume 2: Transceivers
Combining Multiple Channels Configured in Basic (PMA Direct) ×1
Configurations
When you configure a transceiver channel in Basic (PMA Direct) ×1 configuration, the
Quartus II software requires one of the two CMU PLLs within the same transceiver
block to provide high-speed clocks to the transmitter side of the channel (you cannot
use the ATX PLL). Therefore, within a transceiver block, you can only combine a
maximum of five transceiver channels (using both the Transmitter and Receiver)
configured in Basic (PMA Direct) ×1 mode (one CMU channel to perform the clock
multiplication unit functionality).
You can configure the transmitter side of the CMU channel that uses its CMU PLL for
clock generation in Basic (PMA Direct) x1 in single-width or double-width
configuration, as shown in
There are multiple ways you can combine channels in Basic (PMA Direct) ×1 mode
within the same transceiver block:
■
■
■
■
Multiple Basic (PMA Direct) ×1 Configuration Instances with One Channel
per Instance
If you create multiple instances of Basic (PMA Direct) ×1 with one channel per
instance, you can combine them within the same transceiver block. To achieve this
combination, refer to the requirements specified in
CMU PLL” on page 3–5
page
high-speed clock for the transmitter side of the channels. Therefore, at least one CMU
channel (that contains the CMU PLL) within the transceiver block must be available to
generate high-speed serial and low-speed parallel clocks for the channels configured
in this mode. You can also place the individual instances in this configuration in
separate transceiver blocks. For this placement, the Quartus II software enables one
CMU PLL per instance.
One Instance in a Basic (PMA Direct) ×1 Configuration with Multiple
Transceiver Channels
In this case, if the number of channels selected in the instance is less than six, the
Quartus II software, by default, combines these channels within the same transceiver
block and uses one CMU PLL to provide the high-speed clocks. If the number of
channels is six or more, the Quartus II software requires two transceiver blocks and
two CMU PLLs, one from each transceiver block.
The following two examples show the combinations of channels under two different
conditions.
“Multiple Basic (PMA Direct) ×1 Configuration Instances with One Channel per
Instance” on page 3–26
“One Instance in a Basic (PMA Direct) ×1 Configuration with Multiple Transceiver
Channels” on page 3–26
“Combining Multiple Instances of Transmitter Only and Receiver Only
Configurations in Basic (PMA Direct) ×1 Mode” on page 3–29
“Combining Channels Configured in Basic (PMA Direct) ×1 with Non-Basic (PMA
Direct) Modes” on page 3–29
3–3. Note that one CMU PLL within the transceiver block must provide a
and
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Figure 3–17 on page
“General Requirements to Combine Channels” on
Combining Transceiver Channels in Basic (PMA Direct) Configurations
3–32.
“Multiple Channels Sharing a
February 2011 Altera Corporation