DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 333

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 9: Hot Socketing and Power-On Reset in Stratix IV Devices
Power-On Reset Specifications
Power-On Reset Specifications
February 2011 Altera Corporation
f
1
1
Table 9–1
Altera requires powering up V
Table 9–1. Power Supplies Monitored by the POR Circuitry
Table 9–2
Table 9–2. Power Supplies Not Monitored by the POR Circuitry
V
no affect on the device configuration.
The POR specification is designed to ensure that all the circuits in the Stratix IV device
are at certain known states during power up.
The POR signal pulse width is programmable using the PORSEL input pin. When the
PORSEL pin is connected to GND, the POR delay time is 100 to 300 ms. When the
PORSEL pin is set to high, the POR delay time is 4 to 12 ms.
For more information about the POR specification, refer to the
Characteristics in Stratix IV Devices
V
V
V
V
V
V
V
V
V
V
Note to
(1) The transceiver supplies are not monitored by POR.
CCIO
CC
CCPT
CCPD
CCPGM
CCAUX
CCIO
CCA_PLL
CCD_PLL
CC_CLKIN
CCBAT
Power Supply
Power Supply
, V
Table
CCA_PLL
lists the power supplies that the POR circuit monitors.
lists the power supplies that the POR circuit does not monitor.
9–2:
, V
Core and periphery power supply
Programmable power technology power supply
I/O pre-driver power supply
Configuration pins power supply
Auxiliary supply for the programmable power technology
I/O power supply
PLL analog global power supply
PLL digital power supply
PLL differential clock input power supply (top and bottom I/O
banks only)
Battery back-up power supply for design security volatile key
storage
CCD_PLL
, V
CC_CLKIN
CC
before V
chapter.
, and V
Description
Description
CCAUX
CCBAT
.
are not monitored by POR and have
(Note 1)
Stratix IV Device Handbook Volume 1
DC and Switching
1.2, 1.5, 1.8,
1.8, 2.5, 3.0
Setting (V)
Setting (V)
2.5, 3.0
2.5, 3.0
1.2-3.3
0.9
1.5
2.5
2.5
0.9
2.5
9–5