DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 530

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–86
Figure 1–71. Rate Match FIFO Empty Condition in Basic Single-Width Mode
Stratix IV Device Handbook Volume 2: Transceivers
rx_rmfifoempty
1
dataout
datain
Figure 1–71
The rate match FIFO becomes empty after reading out data byte D3.
In Basic double-width mode, the rate match FIFO is capable of compensating up to
±300 PPM (total 600 PPM total) difference between the upstream transmitter and the
local receiver reference clock.
To enable the rate match FIFO in Basic double-width mode, the transceiver channel
must have both the transmitter and receiver channel instantiated. You must select the
Receiver and Transmitter option in the What is the operation mode? field in the
ALTGX MegaWizard Plug-In Manager. You must also enable the 8B/10B
encoder/decoder in Basic double-width mode with rate match FIFO enabled.
Depending on your proprietary protocol implementation, you can select two 20-bit
rate match patterns in the ALTGX MegaWizard Plug-In Manager under the What is
the rate match pattern1 and What is the rate match pattern2 fields. Each of the two
programmed 20-bit rate match patterns consists of a 10-bit skip pattern and a 10-bit
control pattern. You must choose 10-bit code groups that have a neutral disparity as
the skip patterns. The rate match FIFO operation begins after the word aligner
synchronization status rx_syncstatus goes high. When the rate matcher receives
either of the two 10-bit control patterns followed by the respective 10-bit skip pattern,
it inserts or deletes a pair of 10-bit skip patterns as necessary to avoid the rate match
FIFO from overflowing or under running.
The rate match FIFO can delete as many pairs of skip patterns from a cluster
necessary to avoid the rate match FIFO from overflowing. The rate match FIFO can
delete a pair of skip patterns only if the two 10-bit skip patterns appear in the same
clock cycle on the LSByte and MSByte of the 20-bit word. If the two skip patterns
appear straddled on the MSByte of a clock cycle and the LSByte of the next clock
cycle, the rate match FIFO cannot delete the pair of skip patterns. The rate match FIFO
can insert as many pairs of skip patterns into a cluster necessary to avoid the rate
match FIFO from under running. The 10-bit skip pattern can appear on MSByte or
LSByte, or both, of the 20-bit word.
Two flags, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicating rate match
FIFO deletion and insertion events, respectively, are forwarded to the FPGA fabric.
Figure 1–72
skip patterns are required to be deleted. In this example, /K28.5/ is the control
pattern and neutral disparity /K28.0/ is the skip pattern. The first skip cluster has a
/K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte of a
clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle.
Rate Match FIFO in Basic Double-Width Mode
shows the rate match FIFO empty condition in Basic single-width mode.
shows an example of rate match FIFO deletion in the case where three
D1
D1
D2
D2
D3
D3
Chapter 1: Transceiver Architecture in Stratix IV Devices
/K30.7/
D4
D4
D5
February 2011 Altera Corporation
Transceiver Block Architecture
D6
D5