DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 861

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
Figure 5–6. Method 1—Read Transaction Waveform
February 2011 Altera Corporation
logical_address_channel [1:0]
1
rx_tx_duplex_sel [1:0]
In this example, you want to read the existing V
control registers of the transmitter portion of a specific channel controlled by the
ALTGX_RECONFIG instance. For this example, the number of channels connected to
the dynamic reconfiguration controller is four. Therefore, the
logical_channel_address port is 2 bits wide. Also, to initiate the read transaction,
assert the read signal for one reconfig_clk clock cycle. After the read transaction has
completed, the data_valid signal is asserted.
waveform.
Simultaneous write and read transactions are not allowed.
Method 2—Using the Same Control Signals for All Channels
To use Method 2, enable the Use the same control signal for all channels option in
the Analog controls screen of the ALTGX_RECONFIG MegaWizard Plug-In Manager.
Using Method 2, you can write the same PMA control value into all the transceiver
channels connected to the dynamic reconfiguration controller.
The PMA control write ports remain fixed in width irrespective of the number of
channels controlled by the ALTGX_RECONFIG instance. The PMA control read ports
increase in width based on the number of channels controlled by the
ALTGX_RECONFIG instance.
tx_vodctrl [2:0]
reconfig_clk
Read Transaction
data_valid
busy
read
2’b00
2’b00
3’b000
2’b01 (second channel of the ALTGX instance)
2’b10 (transmitter portion only)
Figure 5–6
OD
Stratix IV Device Handbook Volume 2: Transceivers
values from the transmit V
3’bXXX
shows the read transaction
3’b001
OD
5–15