DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 73

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Design Considerations
Design Considerations
February 2011 Altera Corporation
Independent Clock Mode
Input/Output Clock Mode
Read/Write Clock Mode
Single Clock Mode
Selecting TriMatrix Memory Blocks
Stratix IV TriMatrix memory blocks can implement independent clock mode for true
dual-port memories. In this mode, a separate clock is available for each port (clock A
and clock B). Clock A controls all registers on the port A side; clock B controls all
registers on the port B side. Each port also supports independent clock enables for
both port A and port B registers, respectively. Asynchronous clears are supported
only for output latches and output registers on both ports.
Stratix IV TriMatrix memory blocks can implement input/output clock mode for true
dual-port and simple dual-port memories. In this mode, an input clock controls all
registers related to the data input to the memory block including data, address, byte
enables, read enables, and write enables. An output clock controls the data output
registers. Asynchronous clears are available on output latches and output registers
only.
Stratix IV TriMatrix memory blocks can implement read/write clock mode for simple
dual-port memories. In this mode, a write clock controls the data-input,
write-address, and write-enable registers. Similarly, a read clock controls the
data-output, read-address, and read-enable registers. The memory blocks support
independent clock enables for both read and write clocks. Asynchronous clears are
available on data output latches and registers only.
When using read/write clock mode, if you perform a simultaneous read/write to the
same address location, the output read data is unknown. If you require the output
data to be a known value, use either single-clock mode or input/output clock mode
and choose the appropriate read-during-write behavior in the MegaWizard Plug-In
Manager.
Stratix IV TriMatrix memory blocks can implement single-clock mode for true
dual-port, simple dual-port, and single-port memories. In this mode, a single clock,
together with a clock enable, is used to control all registers of the memory block.
Asynchronous clears are available on output latches and output registers only.
This section describes guidelines for designing with TriMatrix memory blocks.
The Quartus II software automatically partitions user-defined memory into
embedded memory blocks by taking into account both speed and size constraints
placed on your design. For example, the Quartus II software may spread memory out
across multiple memory blocks when resources are available to increase the
performance of the design. You can manually assign memory to a specific block size
using the RAM MegaWizard Plug-In Manager.
Stratix IV Device Handbook Volume 1
3–17