DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 324
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 324 of 1154
- Download datasheet (32Mb)
8–46
Document Revision History
Table 8–12. Document Revision History (Part 1 of 2)
Stratix IV Device Handbook Volume 1
February 2011
March 2010
November 2009
June 2009
April 2009
March 2009
Date
Version
Table 8–12
3.0
3.2
3.1
2.3
2.2
2.1
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Updated
Updated the
External PLL Option
Differential Channels”
Applied new template.
Minor text edits.
Removed note 7 from Table 8–1 and Table 8–2.
Updated Figure 8–5.
Updated the “LVDS Channels” section.
Updated Table 8–7.
Added a note to the “LVDS Interface with the Use External PLL Option Enabled” and
“ALTLVDS Port List” sections.
Minor text edits.
Changed “dedicated LVDS” to “true LVDS”.
Removed EP4SE110, EP4SE290, and EP4SE680 devices.
Added EP4SE820 and Stratix IV GT devices.
Updated “LVDS Channels”, “Differential Transmitter”, “Soft-CDR Mode”, and “DPA-
Enabled Channels and Single-Ended I/Os” sections.
Updated Table 8–1, Table 8–2, Table 8–5, and Table 8–6.
Added Table 8–3 and Table 8–4.
Updated Example 8–1.
Updated Figure 8–22.
Minor text edits.
Added an introductory paragraph to increase search ability.
Minor text edits.
Updated “Introduction”.
Updated Figure 8–3.
Removed Table 8-5 and Table 8-6.
Updated “Introduction”, “Stratix IV LVDS Channels”, “Stratix IV Differential Transmitter”,
“Differential I/O Termination”, and “Dynamic Phase Alignment (DPA) Block” sections.
Updated Table 8–1, Table 8–2, Table 8–3, Table 8–4, and Table 8–7.
Added Table 8–5 and Table 8–6.
Updated Figure 8–2.
Removed “Referenced Documents” section.
lists the revision history for this chapter.
Table
“Differential
8–10.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Enabled”, “Deserializer”, and
sections.
Transmitter”,
Changes
“Non-DPA
Mode”,
“Guidelines for DPA-Disabled
“LVDS Interface with the Use
February 2011 Altera Corporation
Document Revision History
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