DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 511
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 511 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–53. Manual Alignment Mode Word Aligner in 16-Bit PMA-PCS Interface Modes
February 2011 Altera Corporation
rx_patterndetect[1:0]
rx_enapatternalign
rx_syncstatus[1:0]
Word aligner operation is controlled by the input signal rx_enapatternalign and is
edge-sensitive to the rx_enapatternalign signal. A rising edge on the
rx_enapatternalign signal triggers the word aligner to look for the word alignment
pattern in the received data stream. The word aligner aligns the 16-bit word boundary
to the first word alignment pattern received after the rising edge on the
rx_enapatternalign signal. Any word alignment pattern received thereafter in a
different word boundary does not cause the word aligner to re-align to this new word
boundary. If another word re-alignment is required, you must de-assert and re-assert
the rx_enapatternalign signal to create a rising edge on this signal.
Two status signals, rx_syncstatus and rx_patterndetect, with the same latency as
the datapath, are forwarded to the FPGA fabric to indicate word aligner status.
After receiving the first word alignment pattern, the rx_patterndetect signal is
driven high for one parallel clock cycle synchronous to the data that matches the
MSByte of the word alignment pattern. Any word alignment pattern received
thereafter in the same word boundary causes rx_patterndetect to go high for one
parallel clock cycle.
After receiving the first word alignment pattern, the rx_syncstatus signal is
constantly driven high until the word aligner sees another rising edge on the
rx_enapatternalign signal. The rising edge on the rx_enapatternalign signal
re-triggers the word alignment operation.
Figure 1–53
PMA-PCS interface mode. In this example, a 16'hF628 is specified as the word
alignment pattern. The word aligner aligns to the 16'hF628 pattern received in cycle n
after de-assertion of rx_digitalreset. The rx_patterndetect[1] signal is driven
high for one parallel clock cycle. The rx_syncstatus[1] signal is driven high
constantly until cycle n + 2, after which it is driven low because of the rising edge on
the rx_enapatternalign signal that re-triggers the word aligner operation. The word
aligner receives the word alignment pattern again in cycle n + 4, causing the
rx_patterndetect[1] signal to be driven high for one parallel clock cycle and the
rx_syncstatus[1] signal to be driven high constantly.
rx_digitalreset
rx_dataout
shows the manual alignment mode word aligner operation in 16-bit
00
00
xxxx
F628
10
10
n
11
n + 1
xxxx
n + 2
xxxx
00
00
xxxx
n + 3
Stratix IV Device Handbook Volume 2: Transceivers
F628
n + 4
10
10
xxxx
11
00
xxxx
1–67
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-5SGXEA7/ES](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: