DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 213

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–29. Differential SSTL I/O Standard Termination
February 2011 Altera Corporation
Termination
External
On-Board
Termination
OCT
Differential I/O Standards Termination
Differential SSTL Class I
Series OCT
Transmitter
Transmitter
1
50 Ω
Stratix IV devices support differential SSTL-18 and SSTL-2, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS.
Figure 6–35
Differential HSTL and SSTL outputs are not true differential outputs. They use two
single-ended outputs with the second output programmed as inverted.
Differential SSTL Class I
25 Ω
25 Ω
Z
Z
50 Ω
50 Ω
0
0
= 50 Ω
= 50 Ω
50 Ω
V TT V TT
show the details of various differential I/O terminations on these devices.
V CCIO
50 Ω
100 Ω
GND
100 Ω
100 Ω
100 Ω
V CCIO
Receiver
Receiver
GND
Series OCT
Differential SSTL Class II
Transmitter
Transmitter
25 Ω
50 Ω
25 Ω
25 Ω
V TT V TT
V TT
V TT
Differential SSTL Class II
50 Ω
50 Ω
Z
Z
0
0
50 Ω
= 50 Ω
= 50 Ω
50 Ω
50 Ω
Stratix IV Device Handbook Volume 1
50 Ω
Figure 6–29
V CCIO
V TT V TT
100 Ω
GND
100 Ω
100 Ω
100 Ω
50 Ω
V CCIO
Receiver
GND
through
Receiver
6–41