DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 738
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 738 of 1154
- Download datasheet (32Mb)
2–66
Figure 2–35. FPGA Fabric-Receiver Interface Clocking in a x4 Bonded Channel Configuration
Note to
(1) The green lines represent low-speed parallel clock from the CMU0 clock divider.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
2–35:
1
Bonded Channel Configuration
All bonded transceiver channel configurations have rate matcher in the receiver data
path. In ×4 and ×8 bonded channel configurations, the Quartus II software
automatically drives the read port of the receiver phase compensation FIFO in all
channels with the coreclkout signal (from the master transceiver block in the case of
×8 bonded mode). Use the coreclkout signal to latch the receiver data and status
signals from all channels in the FPGA fabric.
This configuration uses one FPGA global and/or regional clock resource per bonded
link for the coreclkout signal.
Figure 2–35
configuration.
and Status
and Status
Channel 3
Channel 2
Channel 1
and Status
Channel 0
and Status
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
FPGA
Fabric
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
rx_coreclk[3]
shows the FPGA fabric-Receiver interface clocking in ×4 bonded channel
coreclkout
Reference
Clock
/2
Compensation
Compensation
CMU1
CMU0
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
rdclk
PLL
PLL
RX Phase
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
FIFO
FIFO
FIFO
wrclk
wrclk
wrclk
wrclk
wrclk
Divider
CMU0
Clock
/2
/2
/2
/2
Chapter 2: Transceiver Clocking in Stratix IV Devices
Low-Speed Parallel Clock
from CMU0 Clock Divider
Low-Speed Parallel Clock
from CMU0 Clock Divider
Low-Speed Parallel Clock
from CMU0 Clock Divider
Low-Speed Parallel Clock
from CMU0 Clock Divider
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
CMU1 Channel
CMU0 Channel
Channel 2
Channel 3
Channel 1
FPGA Fabric-Transceiver Interface Clocking
Channel 0
February 2011 Altera Corporation
(Note 1)
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