DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 931
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 931 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 10 of 13)
February 2011 Altera Corporation
Transceiver Channel Reconfiguration Control/Status Signals
reconfig_mode_sel[3:0]
reconfig_address_out[5:0]
reconfig_address_en
reset_reconfig_address
Port Name
Output
Output
Output
Input/
Input
Input
Set the following values at this signal to activate the appropriate
dynamic reconfiguration mode:
3’b000 = PMA controls reconfiguration mode. This is the default
value.
3’b011 = data rate division in transmitter mode
3’b100 = CMU PLL reconfiguration mode
3’b101 = channel and CMU PLL reconfiguration mode
3’b110 = channel reconfiguration with transmitter PLL select mode
3’b111 = central control unit reconfiguration mode
The reconfig_mode_sel signal is 4 bits wide when you enable
Adaptive Equalization control or EyeQ control:
4'b1000 = AEQ control (continuous mode for a single channel)
4'b1001 = AEQ control (one time mode for a single channel)
4'b1010 = AEQ control (power down for a single channel)
4'b1011 = EyeQ control
reconfig_mode_sel[] is available as an input only when you
enable more than one dynamic reconfiguration mode.
This signal is always available for you to select in the Channel and
TX PLL reconfiguration screen. This signal is applicable only in the
dynamic reconfiguration modes grouped under the Channel and
TX PLL select/reconfig option.
This signal represents the current address used by the
ALTGX_RECONFIG instance when writing the .mif into the
transceiver channel. This signal increments by 1, from 0 to the last
address, then starts at 0 again. You can use this signal to indicate
the end of all the .mif write transactions
(reconfig_address_out[5:0] changes from the last address to
0 at the end of all the .mif write transactions).
This is an optional signal you can select in the Channel and TX PLL
reconfiguration screen. This signal is applicable only in dynamic
reconfiguration modes grouped under the Channel and TX PLL
select/reconfig option.
The dynamic reconfiguration controller asserts
reconfig_address_en to indicate that
reconfig_address_out[5:0] has changed. This signal is
asserted only after the dynamic reconfiguration controller
completes writing one 16-bit word of the .mif.
This is an optional signal you can select in the Channel and TX PLL
reconfiguration screen. This signal is applicable only in dynamic
reconfiguration modes grouped under the Channel and TX PLL
select/reconfig option.
Enable this signal and assert it for one reconfig_clk clock cycle if
you want to reset the reconfiguration address used by the
ALTGX_RECONFIG instance during reconfiguration.
Stratix IV Device Handbook Volume 2: Transceivers
Description
(Note
3),
(4)
5–85
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-DEV-2AGX125N](/photos/28/41/284154/dk-dev-2agx125n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
![DK-DEV-3CLS200N](/photos/9/24/92409/dk-dev-3cls200n_tmb.jpg)
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SE530N](/photos/28/41/284157/dk-dev-4se530n_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
![DK-DEV-2AGX260N](/photos/28/41/284175/dk-dev-2agx260n_tmb.jpg)
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
![DK-DEV-5M570ZN](/photos/18/31/183180/dk-dev-5m570zn_tmb.jpg)
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
![DK-DEV-5SGXEA7/ES](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
![DK-DEV-3SL150N](/photos/9/20/92079/dk-dev-3sl150n_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
![DK-DEV-1AGX60N](/photos/9/31/93181/mfgdk-dev-1agx60n_tmb.jpg)
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
![DK-DEV-4CGX150N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
![DK-DEV-4SGX530N](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: