DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 463
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 463 of 1154
- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–6. FPGA Fabric-Transceiver Interface Width and Transceiver PMA-PCS Widths (Part 2 of 2)
February 2011 Altera Corporation
Supported functional modes
Data rate range in Basic functional mode
Name
Transmitter Channel Datapath
The transmitter channel datapath, shown in
following blocks:
■
■
■
■
The Stratix IV GX and GT transceiver provides the Enable low latency PCS mode
option in the ALTGX MegaWizard
8B/10B encoder in the datapath is disabled.
TX Phase Compensation FIFO
The TX phase compensation FIFO interfaces the transmitter channel PCS and the
FPGA fabric PCIe interface. It compensates for the phase difference between the
low-speed parallel clock and the FPGA fabric interface clock. The TX phase
compensation FIFO operates in low-latency and high-latency modes.
Figure 1–14
Figure 1–14. TX Phase Compensation FIFO
TX phase compensation FIFO
Byte serializer
8B/10B encoder
Transmitter output buffer
shows the datapath and clocking of the TX phase compensation FIFO.
Data Path from the FPGA
Fabric or PIPE Interface
tx_coreclk
■
■
■
■
■
■
■
PCIe Gen1 and Gen2
XAUI
GIGE
Serial RapidIO
SONET/SDH OC12 and OC48
SDI
Basic single-width
0.6 Gbps to 3.75 Gbps
Single-Width
wr_clk
™
Compensation
Plug-In Manager. If you select this option, the
TX Phase
FIFO
Figure 1–12 on page
rd_clk
Stratix IV Device Handbook Volume 2: Transceivers
Data Path to the Byte Serializer
■
■
■
or the 8B/10B Encoder or
(OIF) CEI PHY Interface
SONET/SDH OC96
Basic double-width
tx_clkout
coreclkout
Serializer
1 Gbps to 8.5 Gbps
Double-Width
1–17, consists of the
1–19
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