DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 711
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Receiver Channel Datapath Clocking
f
1
Timing may not be met for higher data rates when transceiver channels are
configured in Basic (PMA Direct) functional mode. To meet FPGA fabric-Transmitter
PMA interface timing above certain data rates, you may need to phase shift the
interface clock tx_clkout used to clock the transmitter user logic. To meet FPGA
fabric-Receiver hold time violations, you may have to modify the way data is
captured in the FPGA fabric.
For more information, refer to
Functional
This section describes the receiver PMA and PCS datapath clocking in supported
configurations. Receiver datapath clocking varies between non-bonded and bonded
channel configurations. It also varies with the use of PCS blocks, such as deskew FIFO
and rate matcher. This section describes the following:
■
■
■
Non-Bonded Channel Configurations
In non-bonded channel configurations, receiver PCS blocks of each channel are
clocked independently. Each non-bonded channel also has separate rx_analogreset
and rx_digitalreset signals that allow independent reset of the receiver PCS logic in
each channel.
For more information about transceiver reset and power down signals, refer to the
Reset Control and Power Down in Stratix IV Devices
In non-bonded channel configurations, receiver channel datapath clocking has two
scenarios:
■
■
Non-Bonded Receiver Clocking Without Rate Matcher
The following functional modes have non-bonded receiver channel configuration
without rate matcher:
■
■
■
■
“Non-Bonded Channel Configurations”
“Bonded Channel Configurations” on page 2–43
“Basic (PMA Direct) Mode Channel Configurations” on page 2–49
“Non-Bonded Receiver Clocking Without Rate Matcher”
“Non-Bonded Receiver Clocking with Rate Matcher” on page 2–41
SONET/SDH
SDI
(OIF) CEI PHY Interface
Basic without rate matcher
Meeting Timing in Basic (PMA Direct) Mode
Mode.
AN 580: Achieving Timing Closure in Basic (PMA Direct)
Stratix IV Device Handbook Volume 2: Transceivers
chapter.
2–39
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