DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 162

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–46
Figure 5–40. PLL Reconfiguration Waveform
Stratix IV Device Handbook Volume 1
CONFIGUPDATE
SCANDATAOUT
SCANCLKENA
SCANDONE
SCANDATA
SCANCLK
ARESET
1
D0_old
Figure 5–40
When you reconfigure the counter clock frequency, you cannot reconfigure the
corresponding counter phase shift settings using the same interface. Instead,
reconfigure the phase shifts in real time using the dynamic phase shift reconfiguration
interface. If you reconfigure the counter frequency, but wish to keep the same
non-zero phase shift setting (for example, 90°) on the clock output, you must
reconfigure the phase shift immediately after reconfiguring the counter clock
frequency.
Post-Scale Counters (C0 to C9)
You can reconfigure the multiply or divide values and duty cycle of post-scale
counters in real time. Each counter has an 8-bit high-time setting and an 8-bit
low-time setting. The duty cycle is the ratio of output high- or low-time to the total
cycle time, which is the sum of the two. Additionally, these counters have two control
bits, rbypass, for bypassing the counter, and rselodd, to select the output clock duty
cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a divide by 1.
When the rbypass bit is set to 0, the high- and low-time counters are added to
compute the effective division of the VCO output frequency. For example, if the
post-scale divide factor is 10, the high- and low-count values can be set to 5 and 5,
respectively, to achieve a 50% - 50% duty cycle. The PLL implements this duty cycle
by transitioning the output clock from high to low on the rising edge of the VCO
output clock. However, a 4 and 6 setting for the high- and low-count values,
respectively, produces an output clock with a 40% - 60% duty cycle.
(LSB)
D0
shows a functional simulation of the PLL reconfiguration feature.
(MSB)
Dn_old
Dn
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
Dn
February 2011 Altera Corporation
PLLs in Stratix IV Devices