DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 473

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
Figure 1–25. 8B/10B Encoder Force Current Running Disparity in Double-Width Mode
Transmitter Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be
swapped during board layout. Solutions like a board re-spin or major updates to the
logic in the FPGA fabric can be expensive. The transmitter polarity inversion feature
is provided to correct this situation. An optional tx_invpolarity port is available in
all functional modes except (OIF) CEI PHY to dynamically enable the transmitter
polarity inversion feature.
In single-width mode, a high value on the tx_invpolarity port inverts the polarity of
every bit of the 8-bit or 10-bit input data word to the serializer in the transmitter
datapath. In double-width mode, a high value on the tx_invpolarity port inverts the
polarity of every bit of the 16-bit or 20-bit input data word to the serializer in the
transmitter datapath. Because inverting the polarity of each bit has the same effect as
swapping the positive and negative signals of the differential link, correct data is seen
by the receiver. tx_invpolarity is a dynamic signal and might cause initial disparity
errors at the receiver of an 8B/10B encoded link. The downstream system must be
able to tolerate these disparity errors.
tx_ctrlenable[1:0]
tx_forcedisp[1:0]
Current Running
Disparity
tx_dataout[19:0]
tx_datain[15:0]
tx_dispval[1:0]
clock
17C
RD -
n
BC BC
RD +
283
00
RD -
17C
BC BC
n + 2
11
RD +
283
00
Stratix IV Device Handbook Volume 2: Transceivers
283
RD+
BC
n + 4
01
BC
RD-
17C
RD+
283
BC BC
00
RD-
17C
1–29