DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 269

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
Dynamic On-Chip Termination Control
f
f
1
The ALTMEMPHY megafunction dynamically calibrates the alignment for read- and
write-leveling during the initialization process.
For more information about the ALTMEMPHY megafunction, refer to the
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User
Figure 7–30
needed to dynamically turn on OCT RT during a read and turn OCT RT off during a
write.
For more information about dynamic on-chip termination control, refer to the
Features in Stratix IV Devices
Figure 7–30. Stratix IV Dynamic OCT Control Block
Note to
(1) The write clock comes from either the PLL or the write-leveling delay chain.
Figure
7–30:
shows the dynamic OCT control block. The block includes all the registers
OCT Control Path
OCT Control
OCT Half-
Rate Clock
chapter.
2
HDR
Block
DFF
Write
Clock (1)
Resynchronization
Registers
DFF
OCT Enable
Stratix IV Device Handbook Volume 1
Guide.
External
I/O
7–49