DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 937
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 937 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Duration
February 2011 Altera Corporation
For writing values to the following PMA controls, the busy signal is asserted for 520
reconfig_clk clock cycles per channel for each of these controls:
■
■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 130 reconfig_clk clock cycles per channel for each of these controls. The
data_valid signal is then asserted after the busy signal goes low.
■
■
■
■
For reading the existing values of the following PMA controls, the busy signal is
asserted for 260 reconfig_clk clock cycles per channel for each of these controls. The
data_valid signal is then asserted after the busy signal goes low.
■
■
Offset Cancellation Duration
When the device powers up, the busy signal remains low for the first reconfig_clk
clock cycle. Offset cancellation control is only for the receiver channels. The
ALTGX_RECONFIG instance takes 18500 reconfig_clk clock cycles per channel for
Receiver only and Receiver and Transmitter channels. It takes 900 reconfig_clk
clock cycles per channel for Transmitter only channels to determine if the channel
under reconfiguration is a receiver channel or not. The ATLGX_RECONFIG requires
an additional 130,000 clock cycles for these values to take effect. The
ALTGX_RECONFIG instance takes approximately two reconfig_clk clock cycles per
channel for the unused logical channels.
To demonstrate offset cancellation duration, consider the following example:
■
■
■
For this example, the ALTGX_RECONFIG instance consumes the following number
of reconfig_clk clock cycles for offset cancellation:
■
■
■
The offset cancellation duration for the ALTGX_RECONFIG instance to reconfigure
the Transmitter only channel, Receiver only channel, non-existent logical channels 1,
2, and 3 = 149,406 cycles (900 +18,500 +6 + 130,000).
tx_preemp_0t (pre-emphasis control pre-tap)
tx_preemp_2t (pre-emphasis control second post-tap)
tx_preemp_1t_out (pre-emphasis control first post-tap)
tx_vodctrl_out (voltage output differential)
rx_eqctrl_out (equalizer control)
rx_eqdcgain_out (equalizer DC gain)
tx_preemp_0t_out (pre-emphasis control pre-tap)
tx_preemp_2t_out (pre-emphasis control second post-tap)
One ALTGX_RECONFIG instance is connected to two ALTGX instances.
ALTGX Instance 1 has one Transmitter only channel (logical_channel_address = 0)
ALTGX Instance 2 has one Receiver only channel (logical_channel_address = 4)
900 cycles for the Transmitter only channel
18,500 cycles for the Receiver only channel
2 cycles each for non-existent channels with logical_channel_addresses = 1, 2,
and 3 and 130,000 cycles as a baseline for the values to take affect.
Read Transaction Duration
Stratix IV Device Handbook Volume 2: Transceivers
5–91
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