DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 818

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

4–12
Figure 4–6. Sample Reset Sequence for Eight Receiver and Transmitter Channels—Receiver CDR in Automatic Lock
Mode
Notes to
(1) For t
(2) For t
Stratix IV Device Handbook Volume 2: Transceivers
Figure
pll_powerdown
LTD_Auto
Output Status Signals
4–6:
duration, refer to the
Reset Signals
pll_ powerdown
rx_freqlocked[0]
rx_analogreset
rx_freqlocked[8]
rx _digitalreset
tx_digitalreset
duration, refer to the
pll _ locked
busy
Receiver and Transmitter Channel—Receiver CDR in Automatic Lock Mode
This configuration contains both a transmitter and a receiver channel. For Basic ×8
functional mode, with the receiver CDR in automatic lock mode, use the reset
sequence shown in
1
t
DC and Switching Characteristics for Stratix IV Devices
pll_powerdown (1)
DC and Switching Characteristics for Stratix IV Devices
2
3
Figure
4
Minimum of Two Parallel Clock Cycles
4–6.
5
6
Chapter 4: Reset Control and Power Down in Stratix IV Devices
7
7
t
LTD_Auto (2)
chapter.
chapter.
8
February 2011 Altera Corporation
Transceiver Reset Sequences