DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 705

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Figure 2–19. Two PCIe ×8 Links in Six Transceiver Block Devices
Notes to
(1) Stratix IV devices with six transceiver blocks allow a maximum of two PCIe ×8 links occupying four transceiver blocks. You can configure the
(2) You can use a ×4 PCIe configuration in either a master or slave block.
February 2011 Altera Corporation
other two transceiver blocks to implement other functional modes.
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
Figure
2–19:
Figure 2–19
EP4SGX230KF40, EP4SGX290KF40, EP4SGX360KF40, EP4SGX530KF40
Transceiver Block
Transceiver Block
Transceiver Block
GXBL1 (Slave)
GXBL0(Master)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBL2
shows two PCIe ×8 links in six transceiver block devices.
Second PCIe
x8 Link
First PCIe
x8 Link
(Note 1), (2)
Transceiver Block
Transceiver Block
Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
GXBR0 (Master)
GXBR1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBR2
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
2–33