DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 770
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 770 of 1154
- Download datasheet (32Mb)
3–16
Combining Transceiver Instances Using PLL Cascade Clocks
Stratix IV Device Handbook Volume 2: Transceivers
f
1
For inst1, the ALTGX MegaWizard Plug-In Manager provides a pll_inclk port. In
this example, it is assumed that a single reference clock is provided for inst0 and
inst1. Therefore, connect the pll_inclk port of inst0 and inst1 to the same input
reference clock pin. This enables the Quartus II software to share a single CMU PLL in
transceiver block 1 that has three channels of inst0 and one channel of inst1 (shown
as ch4, ch5, and ch6 in transceiver block 1 in
For the RX CDRs in inst0, the ALTGX MegaWizard Plug-In Manager provides seven
bits for the rx_cruclk port (if you do not select the Train Receiver CDR from
pll_inclk option in the PLL/Ports screen). This allows separate input reference clocks
to the RX CDRs of each channel.
The Stratix IV GX and GT transceiver has the ability to cascade the output of the
general purpose PLLs (PLL_L and PLL_R) to the CMU PLLs, ATX PLLs, and receiver
CDRs. The left side PLLs can only be cascaded with the transceivers on the left side of
the device. Similarly, the right side PLLs can only be cascaded with the transceivers on
the right side of the device. Each side of the Stratix IV GX and GT device contains a
PLL cascade clock network; a single line network that connects the PLL cascade clock
to the transceiver block. This clock line is segmented to allow different PLL cascade
clocks to drive the transceiver CMU PLLs, ATX PLLs, and RX CDRs. Within the same
segment, only a single PLL_L/PLL_R can drive these transceiver PLLs/CDRs.
Therefore, if you create two instances that use different PLLs for cascading, you
cannot place these instances within the transceiver block.
The segmentation locations differ based on the device family.
For more information about using the PLL cascade clock and segmentation, refer to
the “Dedicated Left and Right PLL Cascade Lines Network” section in the
Clocking in Stratix IV Devices
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
chapter.
Combining Transceiver Instances Using PLL Cascade Clocks
Figure
3–6).
February 2011 Altera Corporation
Transceiver
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