DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 746

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–74
Stratix IV Device Handbook Volume 2: Transceivers
Configuration Example 1: Configuring 24 Channels in Basic (PMA Direct)
×N Mode in the EP4S100G5F45 Device
Each transceiver block has four regular channels and two CMU channels that you can
configure in Basic (PMA Direct) ×N mode. The EP4S100G5F45 device has four
transceiver blocks located on each side of the device allowing configuration of up to
24 channels in Basic (PMA Direct) ×N mode.
When all 24 channels on one side of the device are configured in Basic (PMA Direct)
×N mode, all eight CMU channels (two in each transceiver block) are configured as
PMA-Only channels.
Use the refclk pins in each of the four transceiver blocks as receiver serial data input
pins and configure the CMU PLLs as receiver CDRs when the CMU channel is
configured as a PMA-Only channel. Due to the non-availability of CMU PLLs, you
must use the 6G ATX PLL to generate the high-speed serial and low-speed parallel
transceiver clocks for all 24 channels. Due to the non-availability of a refclk pin, you
must use the left and right, or left or right PLL in VCO bypass mode to provide the
reference clock through the PLL cascade clock line.
For more information about left and right PLL VCO bypass mode, refer to
“Configuration Example 4: Configuring Left and Right, Left, or Right PLL in VCO
Bypass Mode” on page
Figure 2–38
configured in Basic (PMA Direct) ×N mode running at 6.5 Gbps with a 20-bit FPGA
fabric-PMA interface width. Because all 24 channels on the right side of the device are
configured in Basic (PMA Direct) ×N mode, the right PLL_R1 configured in
VCO bypass mode is used to provide the input reference clock to the 6G ATX PLL.
The 6G ATX PLL generates the high-speed serial and low-speed parallel transceiver
clocks that are distributed to the 24 channels though the ×N_Top and ×N_Bottom clock
network. Because the data rate of 6.5 Gbps requires a left and right, or left or right PLL
to meet FPGA fabric-Transmitter PMA interface timing, tx_clkout from one of the 24
channels is phase shifted by 315° using PLL_R2. The phase shifted output clock from
PLL_R2 is used to clock the FPGA fabric logic that generates the transmitter parallel
data and control signals.
shows 24 channels on the right side of the EP4S100G5F45 device
2–79.
Chapter 2: Transceiver Clocking in Stratix IV Devices
February 2011 Altera Corporation
Configuration Examples