DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 19

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Overview for the Stratix IV Device Family
Feature Summary
February 2011 Altera Corporation
Stratix IV GT Devices
1
1
Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:
■
■
The actual number of transceiver channels per device varies with device selection. For
more information about the exact transceiver count in each device, refer to
on page
For more information about Stratix IV GT devices and transceiver architecture, refer
to the
Figure 1–3
Figure 1–3. Stratix IV GT Chip View
Note to
(1) Resource counts vary with device selection, package selection, or both.
Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA
circuitry and support data rates between 600 Mbps and 11.3 Gbps
The remaining 16 transceiver channels have dedicated PMA-only circuitry and
support data rates between 600 Mbps and 6.5 Gbps
Figure
Transceiver Architecture in Stratix IV Devices
1–16.
shows a high-level Stratix IV GT chip view.
1–3:
General Purpose I/O and
PLL
PLL
PLL
PLL
with DPA and Soft CDR
High-Speed LVDS I/O
Transceiver Block
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
(Note 1)
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
FPGA Fabric
PLL PLL
PLL PLL
600 Mbps-11.3 Gbps CDR-based Transceiver
General Purpose I/O and up to 1.6 Gbps
LVDS interface with DPA and Soft-CDR
chapter.
General Purpose
I/O and Memory
General Purpose
I/O and Memory
Interface
Interface
Stratix IV Device Handbook Volume 1
PLL
PLL
PLL
PLL
Table 1–7
1–5