DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 620
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 620 of 1154
- Download datasheet (32Mb)
1–176
Figure 1–143. SONET/SDH OC-96 Datapath
Stratix IV Device Handbook Volume 2: Transceivers
tx_coreclk
rx_coreclk
FPGA
Fabric
FPGA Fabric-Transmitter
SONET/SDH OC-96 Datapath
Figure 1–143
mode.
SONET/SDH Transmission Bit Order
Unlike Ethernet, where the LSB of the parallel data byte is transferred first,
SONET/SDH requires the MSB to be transferred first and the LSB to be transferred
last. To facilitate the MSB-to-LSB transfer, you must enable the following options in
the ALTGX MegaWizard Plug-In Manager:
■
■
Depending on whether data bytes are transferred MSB-to-LSB or LSB-to-MSB, you
must select the appropriate word aligner settings in the ALTGX MegaWizard Plug-In
Manager.
transmission order.
Word Alignment
The word aligner in SONET/SDH OC-12, OC-48, and OC-96 modes is configured in
manual alignment mode, as described in
8-Bit PMA-PCS Interface Modes” on page
In OC-12 and OC-48 configurations, you can configure the word aligner to either align
to a 16-bit A1A2 pattern or a 32-bit A1A1A2A2 pattern. This is controlled by the
rx_a1a2size input port to the transceiver. A low level on the rx_a1a2size port
configures the word aligner to align to a 16-bit A1A2 pattern; a high level on the
rx_a1a2size port configures the word aligner to align to a 32-bit A1A1A2A2 pattern.
In OC-96 configuration, the word aligner is only allowed to align to a A1A1A2A2
pattern, so the input port rx_ala2size is unavailable. Barring this difference, the
OC-96 word alignment operation is similar to that of the OC-12 and OC-48
configurations.
FPGA Fabric-Receiver
Interface Clock
Flip transmitter input data bits
Flip receiver output data bits
Interface Clock
Table 1–65 on page 1–177
shows the transceiver datapath when configured in SONET/SDH OC-96
tx_clkout
rx_clkout
Compensation
RX Phase
FIFO
Compensation
wrclk
TX Phase
FIFO
rdclk
wrclk
Serializer
Transmitter Channel PCS
Byte De-
serializer
Byte
/2
lists the correct word aligner settings for each bit
/2
Low-Speed Parallel Clock
Receiver Channel PCS
rdclk
“Word Aligner in Single-Width Mode with
1–60.
Recovered Clock
Chapter 1: Transceiver Architecture in Stratix IV Devices
Parallel
Aligner
Word
Receiver Channel PMA
Transmitter Channel PMA
Serializer
De-
Serializer
Divider
Clock
Local
February 2011 Altera Corporation
CDR
High-Speed
Serial Clock
Transceiver Block Architecture
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