DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 945
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 945 of 1154
- Download datasheet (32Mb)
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Examples
Table 5–19. Logical Channel Addressing Combination ×4 Bonded Channels (Example 2) (Part 2 of 2)
Figure 5–44. Logical Channel Addresses for Example 2
February 2011 Altera Corporation
Settings in Reconfiguration
settings page
reconfig_fromgxb1 and
reconfig_fromgxb2
outputs
Set the What is the number of channels
controlled by the reconfig controller?
ALTGX Setting
ALTGX_RECONFIG Instance
reconfig_fromgxb[16:0] *
ALTGX Settings and Instances
option = 4
Figure 5–44
on what you set as the starting channel number.
■
■
■
■
■
reconfig_fromgxb1 is
17 bits wide
Enable Channel and
Transmitter PLL
reconfiguration
Enable Channel interface
Set 2 for the How many
clock inputs are used?
option.
Set 0 for the XAUI ALTGX
instance.
Set 1 for the PCIe Gen2 ×4
ALTGX instance for the
What is the selected
input clock source for
Tx/Rx PLLs? option.
ALTGX Instance 1
shows how the logical channel addresses of all the channels are set based
(XAUI Mode)
reconfig_fromgxb[16:0]
XAUI/PCI Express (PIPE) Gen2 x4 Functional Mode
reconfig_fromgxb input
ALTGX_RECONFIG Setting
Four regular transceiver channels
(logical channel address = 2)
(logical channel address = 3)
(logical channel address = 1)
(logical channel address = 0)
Starting channel number = 0
ALTGX_RECONFIG Setting and Instance
ALTGX Instance 1
—
Channel 2
Channel 3
Channel 1
Channel 0
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_fromgxb is
17 bits wide
(4 regular transceiver
channels can logically fit into
1 transceiver blocks;
1 * 17 = 17)
ALTGX_RECONFIG
reconfig_togxb[3:0]
Instance 1
—
5–99
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