DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1067

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 3: ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices
Dynamic Reconfiguration
Table 3–3. MegaWizard Plug-In Manager Options (Page 5) (Part 2 of 2)
February 2011 Altera Corporation
Use ‘reconfig_address_out’
Use ‘reconfig_address_en’
Use ‘reset_reconfig_address’
Use ‘logical_tx_pll_sel’
Use ‘logical_tx_pll_sel_en’
ALTGX_RECONFIG Setting
This option is enabled by default when you select the
Channel and TX PLL select/reconfig option. The
value on reconfig_address_out[5:0] indicates
the address associated with the words in the .mif,
which contains the dynamic reconfiguration
instructions. The dynamic reconfiguration controller
automatically increments the address at the end of
each .mif write transaction.
When high, this optional output status signal
indicates that the address used in the .mif write
transaction cycle has changed. This signal is
asserted when the .mif write transaction is
completed (when the busy signal is de-asserted).
When asserted, this optional control signal resets
reconfig_address_out (the current
reconfiguration address) to 0.
This is an optional control signal. The
logical_tx_pll_sel[1:0] signal refers to the
logical reference index of the CMU PLL. The
functionality of the signal depends on the feature
activated, as shown below:
■
■
■
This is an optional control signal. When you enable
this signal, the value set on the
logical_tx_pll_sel[1:0] signal is valid only if
the logical_tx_pll_sel_en is set
to 1.
CMU PLL reconfiguration—The corresponding
CMU PLL is reconfigured based on the value at
logical_tx_pll_sel[1:0].
Channel and CMU PLL reconfiguration—The
corresponding CMU PLL is reconfigured based on
the value at this signal. The transceiver channel
listens to the CMU PLL selected by
logical_tx_pll_sel[1:0].
Channel reconfiguration with TX PLL select—
The transceiver channel listens to the TX PLL
selected by logical_tx_pll_sel[1:0].
Description
“Dynamic Reconfiguration
Controller Port List” section in the
Dynamic Reconfiguration in
Stratix IV Devices
“Dynamic Reconfiguration
Controller Port List” section in the
Dynamic Reconfiguration in
Stratix IV Devices
“Dynamic Reconfiguration
Controller Port List” section in the
Dynamic Reconfiguration in
Stratix IV Devices
“Guidelines for logical_tx_pll_sel
and logical_tx_pll_sel_en Ports”
section in the
Reconfiguration in Stratix IV
Devices
“Guidelines for logical_tx_pll_sel
and logical_tx_pll_sel_en Ports”
section in the
Reconfiguration in Stratix IV
Devices
Stratix IV Device Handbook Volume 3
chapter.
chapter.
Reference
Dynamic
Dynamic
chapter.
chapter.
chapter.
3–11