DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 161

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
Table 5–10. Real-Time PLL Reconfiguration Ports
February 2011 Altera Corporation
scandata
scanclk
scanclkena
configupdate
scandone
scandataout
PLL Port Name
Table 5–10
To reconfigure the PLL counters, follow these steps:
1. The scanclkena signal is asserted at least one scanclk cycle prior to shifting in the
2. Serial data (scandata) is shifted into the scan chain on the second rising edge of
3. After all 234 bits (top and bottom PLLs) or 180 bits (left and right PLLs) have been
4. The configupdate signal is asserted for one scanclk cycle to update the PLL
5. The scandone signal goes high, indicating the PLL is being reconfigured. A falling
6. Reset the PLL using the areset signal if you make any changes to the M, N, or
7. You can repeat steps 1-5 to reconfigure the PLL any number of times.
Serial input data stream to scan
chain.
Serial clock input signal. This clock
can be free running.
Enables scanclk and allows the
scandata to be loaded in the scan
chain. Active high.
Writes the data in the scan chain to
the PLL. Active high.
Indicates when the PLL has finished
reprogramming. A rising edge
indicates the PLL has begun
reprogramming. A falling edge
indicates the PLL has finished
reprogramming.
Used to output the contents of the
scan chain.
first bit of scandata (D0).
scanclk.
scanned into the scan chain, the scanclkena signal is de-asserted to prevent
inadvertent shifting of bits in the scan chain.
counters with the contents of the scan chain.
edge indicates the PLL counters have been updated with new settings.
post-scale output C counters or to the Icp, R, or C settings.
lists how these signals can be driven by the PLD logic array or I/O pins.
Description
Logic array or I/O pin
GCLK, RCLK or I/O pins
Logic array or I/O pin
Logic array or I/O pin
PLL reconfiguration circuit
PLL reconfiguration circuit
Source
Stratix IV Device Handbook Volume 1
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
PLL reconfiguration circuit
Logic array or I/O pins
Logic array or I/O pins
Destination
5–45