DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 618
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
1–174
Figure 1–140. SONET/SDH Mode Configurations in Stratix IV GX and GT Devices
Note to
(1) This is not supported in Stratix IV GT devices.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
PMA-PCS Interface
Interface Frequency
Functional Modes
Encoder/Decoder
Fabric-Transceiver
Fabric-Transceiver
Data Rate (Gbps)
Rate Match FIFO
Functional Mode
Channel Bonding
Low-Latency PCS
TX PCS Latency
Interface Frequency
RX PCS Latency
(Pattern Length)
Byte Ordering
Interface Width
Byte SerDes
Word Aligner
8B/10B
1–41:
Width
FPGA
FPGA
(MHz)
Figure 1–140
Stratix IV GX and GT devices.
8-bit
Single
Width
10-bit
Basic
shows SONET/SDH mode configurations supported in
16-bit
0.622 (OC-12) (1)
Double
32-Bit A1A1A2A2)
Manual Alignment
Width
(16-Bit A1A2,
Disabled
Disabled
Disabled
Disabled
Disabled
Stratix IV GX and GT Configurations
11 - 13
77.75
8-Bit
5 - 6
x1
20-bit
10-bit
PIPE
10-bit
XAUI
SONET/
SDH
GIGE
10-bit
Manual Alignment
32-Bit A1A1A2A2)
2.488 (OC-48)
Protocol
SRIO
10-bit
(16-Bit A1A2,
Chapter 1: Transceiver Architecture in Stratix IV Devices
Disabled
Disabled
Disabled
Enabled
Enabled
16-Bit
155.5
4 - 5.5
7 - 9
x1
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
10-bit
SDI
February 2011 Altera Corporation
10-Bit
Transceiver Block Architecture
Deterministic
Latency
(32-Bit A1A1A2A2)
Manual Alignment
4.976 (OC-96)
20-Bit
Disabled
Disabled
Disabled
Enabled
Disabled
4 - 5.5
32-Bit
155.5
6.5 -
x1
8.5
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