DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 1038
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 1038 of 1154
- Download datasheet (32Mb)
2–20
Table 2–6. Configuring Clocking (Part 2 of 2)
Figure 2–3. Top-Level Transceiver Setup—Transmitter-Side Only
Stratix IV Device Handbook Volume 3
Can transceiver-FPGA fabric interface clocking be shared?
Does the Stratix IV GX transceiver support this feature?
refclk1 (53.125 MHz)
refclk0 (106.25 MHz)
f
1
For more information about clocking the transmitter and receiver channel data path
for this type of configuration, refer to the “Transmitter Channel Datapath Clocking”
section of the
Figure 2–3
The transmitter side receives its clocks from the clock multiplier unit (CMU) PLLs.
The receiver side contains its dedicated CDR that provides the high-speed serial and
low-speed parallel clocks to its PMA and PCS blocks, respectively.
Questions
shows the transmitter side of the transceiver setup for Example 1.
Second CMU PLL Configured for
Transceiver Clocking in Stratix IV Devices
One CMU PLL Configured for
1.0625 Gbps Data Rate
4.25 Gbps Data Rate
Transceiver Block
No
The design requires independent control on all channels, so
you must not share the transceiver-FPGA fabric interface
clock of one channel with another channel. Each of the
channels must use its own tx_clkout and rx_clkout
signals to clock the data between the transceiver channels and
the FPGA fabric.
Yes
Chapter 2: Transceiver Design Flow Guide for Stratix IV Devices
Example 1: Fibre Channel Protocol Application
chapter.
Answer
(1.0625 Gbps)
(4.25 Gbps)
(4.25 Gbps)
February 2011 Altera Corporation
Channel 1
Channel 2
Channel 0
TX
TX
RX
RX
TX
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