DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 564

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–120
Figure 1–101. Transceiver Configurations in Basic Double-Width Mode with a 20-Bit PMA-PCS Interface for Stratix IV GT
Devices
Notes to
(1) The maximum data rate specification shown in
(2) The circled configuration supports data rates up to 11.3 Gbps per channel to implement 40G/100G links.
Stratix IV Device Handbook Volume 2: Transceivers
other speed grades offered, refer to the
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
Interface Clock Cycles)
Interface Clock Cycles)
(1)
(1)
Figure
TX PCS Latency
Interface Frequency
RX PCS Latency
Interface Frequency
Interface Frequency
Data Rate (Gbps)
Low-Latency PCS
Channel Bonding
Rate Match FIFO
Encoder /Decoder
Interface Width
(Pattern Length )
FPGA Fabric -
FPGA Fabric -
Interface Width
FPGA Fabric -
Byte Ordering
PMA
Transceiver
Transceiver
Word Aligner
Byte SerDes
Transceiver
Interface Width
PMA-PCS
Data Rate
( MHz )
Functional
8B/10B
Modes
PCS/Fabric
1–101:
f
-
Disabled
Disabled
For more information about 40G/100G transceivers, refer to:
124.4 -
10 - 12
8-bit
1.0 -
20-bit
325
6.5
5 - 6
Single
Width
Disabled
Disabled
■
■
■
Disabled
6.5 - 8.5
10-bit
62.2 -
212.5
4 - 5.5
40-bit
Enabling 40G/100G Solutions with FPGAs with 11.3-Gbps Transceivers
cast
Stratix IV FPGA 40G/100G IP Solutions
AN 570: Implementing the 40G/100G Ethernet Protocol in Stratix IV Devices
Basic
Enabled
1.0 -
8.5
16-bit
6.5 - 8.5
Enabled
62.2 -
212.5
4 - 5.5
40-bit
Manual Alignment
(7-, 10-, 20-bit)
Double
Width
DC and Switching Characteristics
20-bit
Stratix IV GT Configurations
Disabled
Disabled
124.4 -
10 - 12
1.0 -
16-bit
5 - 6
5.0
250
Figure 1–101
Disabled
Disabled
6.5 - 8. 5
62.2 -
212.5
4 - 5.5
32-bit
Enabled
1.0 -
8.5
Enabled
6.5 - 8. 5
Enabled
62.2 -
32-bit
212.5
4 - 5.5
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Disabled
Disabled
124.4 -
22 - 26
1.0 -
16-bit
5.0
5 - 6
250
Disabled
Enabled
PIPE
10-bit
Disabled
Enabled
13 - 16
62.2 -
212.5
32-bit
1.0 -
4 - 5.5
8.5
chapter.
XAUI
10-bit
600 Mbps - 11.3 Gbps
Basic Double Width
20-bit PMA-PCS
Protocol
Interface Width
Disabled
Disabled
SRIO
10-bit
124.4 -
20-bit
10 - 12
1.0 -
325
6.5
5 - 6
x1, x4, x8
Disabled
Disabled
Chapter 1: Transceiver Architecture in Stratix IV Devices
SONET
/SDH
8-bit
6.5 - 8. 5
Enabled
Disabled
(7-, 10-, 20-bit)
62.2 -
212.5
4 - 5.5
1.0 -
40-bit
8.5
Bit-Slip
website
16-bit
(OIF)
CEI
Disabled
Disabled
10 - 12
124.4 -
1.0 -
16-bit
5 - 6
5.0
250
Disabled
Enabled
10-bit
SDI
6.5 - 8. 5
Enabled
Disabled
62.2 -
212.5
1.0 -
32-bit
4 - 5.5
8.5
10-Bit
Deterministic
Latency
February 2011 Altera Corporation
20-Bit
Transceiver Block Architecture
Disabled
2.488 -
Disabled
124.4 -
20-bit
6.5
4 - 5
325
3 - 4
Disabled
Disabled
Disabled
Enabled
2.488 -
Enabled
Disabled
11.3
62.2 -
282.5
40-bit
4 - 5.5
3 - 4.5
(2)
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