DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 42

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

2–6
Figure 2–5. High-Level Block Diagram of the Stratix IV ALM
Stratix IV Device Handbook Volume 1
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, an ALM can
efficiently implement various arithmetic functions and shift registers. Each ALM
drives all types of interconnects: local, row, column, carry chain, shared arithmetic
chain, register chain, and direct link.
the Stratix IV ALM.
Combinational/Memory ALUT1
Combinational/Memory ALUT0
shared_arith_out
shared_arith_in
6-Input LUT
6-Input LUT
carry_in
carry_out
adder0
adder1
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
Figure 2–5
reg_chain_in
reg_chain_out
labclk
shows a high-level block diagram of
D
D
reg0
reg1
Q
Q
February 2011 Altera Corporation
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
Adaptive Logic Modules