DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 643

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Auxiliary Transmit (ATX) PLL Block
Figure 1–165. ATX PLL Block
Notes to
(1) In non-bonded functional modes (for example, CEI functional mode), the transmitter channel uses the transmitter local clock divider to divide this
(2) This is used in Basic ×4, ×8, and PCIe ×4 and ×8 functional modes.
February 2011 Altera Corporation
cascaded PLL clock
ITB clock lines
high-speed clock output to provide clocks for its PMA and PCS blocks.
global clock line
PCIErateswitch
pll_powerdown
Figure
Architecture of the ATX PLL Block
8
1–165:
f
1
For the 10G ATX PLL, Stratix IV GT devices only allow driving the reference clock
source from one of the dedicated reflck pins on the same side of the device.
For improved jitter performance, Altera strongly recommends using the REFCLK pins
of the transceiver block located immediately below the 10G ATX PLL block to drive
the input reference clock.
For more information about the input reference clocks for ATX PLLs, refer to the
Transceiver Clocking for Stratix IV Devices
Figure 1–165
and a shared control signal generation block).
The functional blocks on the ATX PLL are similar to the blocks explained in
PLL” on page
automatically selected by the Quartus II software based on the transceiver channel
configuration.
The ATX PLL high-speed clock output provides high-speed serial clocks for
non-bonded functional modes such as CEI (with the “none” subprotocol).
reference clock
ATX PLL input
shows the ATX PLL block components (the ATX PLL, ATX clock divider,
1–102. The values of the /M and /L divider settings in the ATX PLL are
ATX PLL
PCI Express
rate switch
high-speed
controller
ATX PLL
Clock (1)
PCIE_gen2switch
chapter.
PCIE_gen2switch_done
divider block
Stratix IV Device Handbook Volume 2: Transceivers
ATX clock
ATX PLL Block
high-speed serial clock
for bonded modes (2)
“CMU0
1–199