DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 565

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
February 2011 Altera Corporation
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SATA and SAS Options
Serial advanced technology attachment (SATA) and serial attached SCSI (SAS) are
computer bus standards used in computers to transfer data between a mother board
and mass storage devices. Stratix IV GX and GT devices offer options to implement a
transceiver that satisfies SATA and SAS protocols. These options are:
■
■
These options and their selections are described in the following sections.
In Basic functional mode, you can enable the optional input signal tx_forceelecidle.
When this input signal of a channel is asserted high, the transmitter buffer in that
channel is placed in the electrical idle state. During electrical idle, the output of the
transmitter buffer is tri-stated.
This signal is used in applications such as SATA and SAS for generating out of band
(OOB) signals. An OOB signal is a pattern of idle times and burst times. Different
OOB signals are distinguished by their different idle times.
Manual CDR lock mode is required because you must be in lock-to-reference mode
during OOB signaling.
For more information about the transmitter buffer in the Electrical Idle state, refer to
the “Transmitter Buffer Electrical Idle” section in
In Basic functional mode, you can enable the optional rx_signaldetect signal (used
for protocols such as SATA and SAS) only if you select the 8B/10B block. When you
select the optional rx_signaldetect signal, an option is available to set the desired
threshold level of the signal being received at the receiver ’s input buffer. If the signal
threshold detection circuitry senses the signal level present at the receiver input buffer
to be higher than the chosen signal detect threshold, it asserts the rx_signaldetect
signal high. Otherwise, the signal threshold detection circuitry de-asserts the
rx_signaldetect signal low. This signal is useful in applications such as SATA and
SAS for detecting OOB signals.
For more information on the signal threshold detection circuitry, refer to the “Signal
Threshold Detection Circuitry” section in
chapter.
For information about other protocols supported using Basic functional mode, refer to
AN 577: Recommended Protocol Configurations for Stratix IV
Transmitter in electrical idle mode
Receiver signal detect functionality
Transmitter Buffer Electrical Idle
Receiver Input Signal Detect
Transceiver Architecture in Stratix IV Devices
Stratix IV Device Handbook Volume 2: Transceivers
“PCIe Mode” on page
FPGAs.
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