DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 908

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–62
Figure 5–32. Local Divider of a Transmitter Channel
Stratix IV Device Handbook Volume 2: Transceivers
High-Speed clock
High-Speed clock
from TX PLL1
from TX PLL0
1
Data Rate Division in Transmitter Mode Details
You can use data rate division in transmitter mode to modify the data rate of the
transmitter channel in multiples of 1, 2, and 4. This dynamic reconfiguration mode is
available only for the transmit side and not for the receive side.
Blocks Reconfigured in the Data Rate Division in Transmitter Mode
The only block that is reconfigured by the data rate division in transmitter mode is the
transmitter local divider block of a transmitter channel. You can set the transmitter
local divider to a divide by value of /1, /2, or /4, as shown in
You must be aware of the device operating range before you enable and use this
feature. There are no legal checks that are imposed by the Quartus II software because
it is an on-the-fly control feature. You must ensure that a specific functional mode
supports the data rate range before dividing the clock when using this rate switch
option.
Data rate division in transmitter mode is applicable only to channels configured in
non-bonded mode clocked by the CMU0/CMU1 located within the same transceiver
block.
ALTGX MegaWizard Plug-In Manager Setup for Data Rate Division in Transmitter Mode
Enable the following settings in the ALTGX MegaWizard Plug-In Manager:
1. Select the Channel and Transmitter PLL Reconfiguration option in the Reconfig
2. Set the What is the starting channel number? option in the Reconfig screen. For
The alternate reference clock is not required because a single clock source is used. The
/1, /2, or /4 data rates can be derived from the single input reference clock.
screen to enable the ALTGX_RECONFIG instance to modify the transmitter
channel local divider values dynamically.
more information, refer to
/1, /2, or /4
/n
“Logical Channel Addressing” on page
/4, /5, /8, or /10
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
Figure
High-Speed Serial Clock
Low-Speed Parallel Clock
5–32.
5–5.