DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 843
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 843 of 1154
- Download datasheet (32Mb)
Chapter 4: Reset Control and Power Down in Stratix IV Devices
Dynamic Reconfiguration Reset Sequences
February 2011 Altera Corporation
Reset Sequence when Using Dynamic Reconfiguration with the ‘Channel
and TX PLL select/reconfig’ Option
Use the example reset sequence shown in
dynamic reconfiguration controller to change the TX PLL settings of the transceiver
channel. In this example, the dynamic reconfiguration is used to dynamically
reconfigure the data rate of the transceiver channel configured in Basic ×1 mode with
receiver CDR in automatic lock mode.
Figure 4–21. Reset Sequence When Using the Dynamic Reconfiguration Controller to Change the
TX PLL Settings of the Transceiver Channel
Note to
(1) For t
As shown in
change the configuration of the transceiver channel, follow these reset steps:
1. After power up and establishing that the transceiver is operating as desired, write
2. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset signals.
3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to
4. Wait for the assertion of the channel_reconfig_done signal (marker 4) that
the desired new value in the appropriate registers (including
reconfig_mode_sel[2:0]) and subsequently assert the write_all signal
(marker 1) to initiate the dynamic reconfiguration.
f
execute its operation. This is indicated by the assertion of the busy signal
(marker 2).
indicates the completion of dynamic reconfiguration in this mode.
Reset and Control Signals
Figure
reconfig_mode_sel[2:0]
LTD_Auto
channel_reconfig_done
Ouput Status Signals
For more information, refer to the
Devices
4–21:
rx_analogreset
rx_digitalreset
tx_digitalreset
rx_freqlocked
duration, refer to the
Figure
write_all
busy
chapter.
4–21, when using the dynamic reconfiguration controller to
New value
1
1
1
1
DC and Switching Characteristics for Stratix IV Devices
2
3
Figure 4–21
Dynamic Reconfiguration in Stratix IV
4
Five parallel clock cycles
5
Stratix IV Device Handbook Volume 2: Transceivers
6
7
t
LTD_Auto (1)
when you are using the
8
chapter.
4–37
Related parts for DK-DEV-4SGX230N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
KIT DEV ARRIA II GX FPGA 2AGX125
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV CYCLONE III LS EP3CLS200
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX IV FPGA 4SE530
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV FPGA 2AGX260 W/6.375G TX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV MAX V 5M570Z
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV STRATIX V FPGA 5SGXEA7
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX III
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEV ARRIA GX 1AGX60N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT STARTER CYCLONE IV GX
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
KIT DEVELOPMENT STRATIX IV
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: