DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 408

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

11–2
Error Detection Fundamentals
Configuration Error Detection
User Mode Error Detection
Stratix IV Device Handbook Volume 1
1
Error detection determines whether the data received is corrupted during
transmission. To accomplish this, the transmitter uses a function to calculate a
checksum value for the data and appends the checksum to the original data frame.
The receiver uses the same calculation methodology to generate a checksum for the
received data frame and compares the received checksum to the transmitted
checksum. If the two checksum values are equal, the received data frame is correct
and no data corruption occurred during transmission or storage.
The error detection CRC feature uses the same concept. When Stratix IV devices are
configured successfully and are in user mode, the error detection CRC feature ensures
the integrity of the configuration data.
There are two CRC error checks. One CRC error check always runs during
configuration and a second optional CRC error check runs in the background in user
mode. Both CRC error checks use the same CRC polynomial but different error
detection implementations. For more information, refer to
Detection”
In configuration mode, a frame-based CRC is stored within the configuration data
and contains the CRC value for each data frame.
During configuration, the Stratix IV device calculates the CRC value based on the
frame of data that is received and compares it against the frame CRC value in the data
stream. Configuration continues until either the device detects an error or
configuration is completed.
In Stratix IV devices, the CRC value is calculated during the configuration stage. A
parallel CRC engine generates 16 CRC check bits per frame and then stores them in
CRAM. The CRAM chain used for storing the CRC check bits is 16 bits wide and its
length is equal to the number of frames in the device.
Stratix IV devices have built-in error detection circuitry to detect data corruption by
soft errors in the CRAM cells. This feature allows all CRAM contents to be read and
verified to match a configuration-computed CRC value. Soft errors are changes in a
CRAM bit state due to an ionizing particle.
The error detection capability continuously computes the CRC of the configured
CRAM bits and compares it with the pre-calculated CRC. If the CRCs match, there is
no error in the current configuration CRAM bits. The process of error detection
continues until the device is reset (by setting nCONFIG low).
If you enable the CRC error detection option in the Quartus II software, after the
device transitions into user mode, the error detection process is enabled. The internal
100 MHz configuration oscillator is divided down by a factor of two to 256 (at powers
of two) to be used as the clock source during the error detection process. You must set
the clock divide factor in the Quartus II software.
and
“User Mode Error
Detection”.
Chapter 11: SEU Mitigation in Stratix IV Devices
“Configuration Error
February 2011 Altera Corporation
Error Detection Fundamentals