DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 22
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 22 of 1154
- Download datasheet (32Mb)
1–8
Stratix IV Device Handbook Volume 1
FPGA Fabric and I/O Features
The following sections describe the Stratix IV FPGA fabric and I/O features.
Device Core Features
■
■
■
■
Embedded Memory
■
■
■
Digital Signal Processing (DSP) Blocks
■
■
■
Clock Networks
■
■
■
■
Up to 531,200 LEs in Stratix IV GX and GT devices and up to 813,050 LEs in
Stratix IV E devices, efficiently packed in unique and innovative adaptive logic
modules (ALMs)
Ten ALMs per logic array block (LAB) deliver faster performance, improved logic
utilization, and optimized routing
Programmable power technology, including a variety of process, circuit, and
architecture optimizations and innovations
Programmable power technology available to select power-driven compilation
options for reduced static power consumption
TriMatrix embedded memory architecture provides three different memory block
sizes to efficiently address the needs of diversified FPGA designs:
■
■
■
Up to 33,294 Kbit of embedded memory operating at up to 600 MHz
Each memory block is independently configurable to be a single- or dual-port
RAM, FIFO, ROM, or shift register
Flexible DSP blocks configurable as 9 × 9-bit, 12 × 12-bit, 18 × 18-bit, and
36 × 36-bit full-precision multipliers at up to 600 MHz with rounding and
saturation capabilities
Faster operation due to fully pipelined architecture and built-in addition,
subtraction, and accumulation units to combine multiplication results
Optimally designed to support advanced features such as adaptive filtering, barrel
shifters, and finite and infinite impulse response (FIR and IIR) filters
Up to 16 global clocks and 88 regional clocks optimally routed to meet the
maximum performance of 800 MHz
Up to 112 and 132 periphery clocks in Stratix IV GX and Stratix IV E devices,
respectively
Up to 66 (16 GCLK + 22 RCLK + 28 PCLK) clock networks per device quadrant in
Stratix IV GX and Stratix IV GT devices
Up to 71 (16 GCLK + 22 RCLK + 33 PCLK) clock networks per device quadrant in
Stratix IV E devices
640-bit MLAB
9-Kbit M9K
144-Kbit M144K
Chapter 1: Overview for the Stratix IV Device Family
February 2011 Altera Corporation
Architecture Features
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