DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 447

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Overview
Figure 1–1. Example of a Transceiver Block
February 2011 Altera Corporation
Transceiver Block
Transceiver Block
ATX PLL Block
Calibration Block
Calibration Block
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
GXBL1
GXBL0
8
9
9
Figure 1–1
Links to the corresponding transceiver architecture descriptions are listed below. This
is an elementary diagram and does not represent an actual transceiver block.
Descriptions for the example transceiver architecture are as follows:
1.
2.
3.
4.
5.
6.
7.
8.
Calibration Block
Calibration Block
“Transceiver Block Architecture” on page 1–16
“Transceiver Channel Architecture” on page 1–17
“Transmitter Channel Datapath” on page 1–19
“Transmitter Local Clock Divider Block” on page 1–39
“Receiver Channel Datapath” on page 1–40
“CMU Channel Architecture” on page 1–100
“Loopback Modes” on page 1–190
“Auxiliary Transmit (ATX) PLL Block” on page 1–195
ATX PLL Block
Transceiver Block
Transceiver Block
GXBR1
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
GXBR0
shows an example of the Stratix IV GX and GT transceiver architecture.
8
9
9
Unit (CCU)
Central
Control
Local Clock Divider Block
Transceiver Channel 2
Transceiver Channel 3
1
Transceiver Block
BIST
Transceiver Channel 0
BIST
Transceiver Channel 1
BIST
BIST
10
10
10
10
Loopback
Loopback
Loopback
Loopback
CMU1 Channel
CMU0 Channel
Stratix IV Device Handbook Volume 2: Transceivers
7
7
2
7
1
2
7
2
2
4
6
6
Receiver Channel Datapath
Transmitter Channel Datapath
5
3
1–3