DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 878

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–32
Figure 5–18. Option 2 for Transmitter Core Clocking (Channel and CMU PLL Reconfiguration Mode)
Stratix IV Device Handbook Volume 2: Transceivers
FPGA Fabric
tx_clkout[0]
tx_clkout[1]
tx_clkout[2]
tx_clkout[3]
1
High-speed serial clock generated by the CMU0 PLL
Low-speed parallel clock generated by the local divider of the transceiver
Figure 5–18
to the Transmit Phase Compensation FIFOs of the respective transceiver channels.
Receiver core clocking refers to the clock that is used to read the parallel data from the
Receiver Phase Compensation FIFO into the FPGA fabric. You can use one of the
following clocks to read from the Receive Phase Compensation FIFO:
■
■
The Clocking/Interface screen is not available for PMA-only channels.
rx_coreclk—You can use a clock of the same frequency as rx_clkout from the
FPGA fabric to provide the read clock to the Receive Phase Compensation FIFO. If
you use rx_coreclk, it overrides the rx_clkout options in the ALTGX
MegaWizard Plug-In Manager.
rx_clkout—The Quartus II software automatically routes rx_clkout to the FPGA
fabric and back into the Receive Phase Compensation FIFO.
shows how each transmitter channel’s tx_clkout signal provides a clock
TX0 (3 Gbps/1.5 Gbps)
TX1 (3 Gbps/6 Gbps)
TX2 (3 Gbps/1.5 Gbps)
TX3 (3 Gbps)
Transciever Block
RX1
RX2
RX3
RX0
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
CMU1 PLL
CMU0 PLL
February 2011 Altera Corporation