DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 543

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–37. Receiver Phase Compensation FIFO Write Clock Source
Table 1–38. Receiver Phase Compensation FIFO Read Clock Source
February 2011 Altera Corporation
Non-bonded channel
configuration with rate matcher
Non-bonded channel
configuration without rate
matcher
×4 bonded channel configuration
×8 bonded channel configuration
Non-bonded channel
configuration with rate matcher
Non-bonded channel
configuration without rate
matcher
×4 bonded channel configuration
×8 bonded channel configuration
Note to
(1) The clock signal driven on the rx_coreclk port must have 0 PPM frequency difference with respect to the receiver phase compensation FIFO
write clock.
Table
Configuration
Configuration
1–38:
The receiver phase compensation FIFO write clock source varies with the receiver
channel configuration.
clock source in different configurations.
The receiver phase compensation FIFO read clock source varies depending on
whether or not you instantiate the rx_coreclk port in the ALTGX MegaWizard
Plug-In Manager.
source in different configurations.
Parallel transmitter PCS clock from the
local clock divider in the associated
channel (tx_clkout)
Parallel recovered clock from the receiver
PMA in the associated channel
(rx_clkout)
Parallel transmitter PCS clock from the
central clock divider in the CMU0 of the
associated transceiver block
(coreclkout)
Parallel transmitter PCS clock from the
central clock divider in CMU0 of the master
transceiver block (coreclkout from
master transceiver block)
FPGA fabric clock driven by the clock
signal on the tx_clkout port
FPGA fabric clock driven by the clock
signal on the rx_clkout port
FPGA fabric clock driven by the clock
signal on the coreclkout port
FPGA fabric clock driven by the clock
signal on the coreclkout port
rx_coreclk Port Not Instantiated
Table 1–38
Without Byte Serializer
Table 1–37
Receiver Phase Compensation FIFO Write Clock
Receiver Phase Compensation FIFO Read Clock
lists the receiver phase compensation FIFO read clock
lists the receiver phase compensation FIFO write
Stratix IV Device Handbook Volume 2: Transceivers
Divide-by-two version of the parallel
transmitter PCS clock from the local clock
divider in the associated channel
(tx_clkout)
Divide-by-two version of the parallel
recovered clock from the receiver PMA in
the associated channel (rx_clkout)
Divide-by-two version of the parallel
transmitter PCS clock from the central
clock divider in CMU0 of the associated
transceiver block (coreclkout)
Divide-by-two version of the parallel
transmitter PCS clock from the central
clock divider in CMU0 of the master
transceiver block (coreclkout from
master transceiver block)
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
FPGA fabric clock driven by the clock
signal on the rx_coreclk port
rx_coreclk Port Instantiated
With Byte Serializer
(1)
1–99