DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 654

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

1–210
Table 1–73. Stratix IV GX and GT ALTGX Megafunction Ports: Transmitter Ports (Part 2 of 3)
Stratix IV Device Handbook Volume 2: Transceivers
8B/10B Encoder
tx_ctrlenable
tx_forcedisp
tx_dispval
Port Name
Output
Input/
Input
Input
Input
pulse width is two
pulse width is two
signal. Minimum
signal. Minimum
Synchronous to
Asynchronous
Asynchronous
Clock Domain
parallel clock
parallel clock
tx_clkout/
coreclkout
clock signal.
cycles.
cycles.
8B/10B encoder /Kx.y/ or /Dx.y/ control.
■
■
■
8B/10B encoder force disparity control.
■
■
■
8B/10B encoder force disparity value.
■
■
■
When asserted high—the 8B/10B encoder
encodes the data on the tx_datain port as
a /Kx.y/ control code group.
When de-asserted low—it encodes the data
on the tx_datain port as a /Dx.y/ data code
group.
Channel Width:
8—tx_ctrlenable = 1
16—tx_ctrlenable = 2
32—tx_ctrlenable = 4
When asserted high—forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive or negative
disparity depending on the tx_dispval
signal level.
When de-asserted low—the 8B/10B encoder
encodes the data on the tx_datain port
according to the 8B/10B running disparity
rules.
Channel Width:
8—tx_forcedisp = 1
16—tx_forcedisp = 2
32—tx_forcedisp = 4
A high level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a negative starting
running disparity.
A low level—when the tx_forcedisp
signal is asserted high, it forces the 8B/10B
encoder to encode the data on the
tx_datain port with a positive starting
running disparity.
Channel Width:
8—tx_dispval = 1
16—tx_dispval = 2
32—tx_dispval = 4
Chapter 1: Transceiver Architecture in Stratix IV Devices
Description
February 2011 Altera Corporation
Transceiver Port Lists
Channel
Channel
Channel
Scope