DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 987
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
- Current page: 987 of 1154
- Download datasheet (32Mb)
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Reconfiguration Settings
Table 1–7. MegaWizard Plug-In Manager Options (Modes Screen) (Part 2 of 2)
February 2011 Altera Corporation
How many input clocks are
used?
What is the starting channel
number?
ALTGX Setting
Transmitter PLL Settings
1
Depending on the number of additional PLLs you select in the How many additional
PLLs are used? option in Reconfiguration Settings, the corresponding PLL screens
become available.
Each of these PLL screens have the same settings available for selection.
each of these settings.
The Main PLL is the PLL you configure in the General screen. Therefore, some of the
options are already enabled or disabled for this PLL. Some of the options differ when
compared with the additional transmitter PLLs.
Enter the number of input clocks available for selection for
the transmitter PLLs and receiver PLL. You have a choice of
up to 10 input clock sources (clock 1, clock 2, and so on).
You must set the starting channel number of the first ALTGX
instance controlled by the dynamic reconfiguration controller
to 0. Set the starting channel number of the consecutive
ALTGX instances controlled by the same dynamic
reconfiguration controller, if any, in the next available
multiples of 4.
Description
Stratix IV Device Handbook Volume 3
“Guidelines for Specifying
the Input Reference Clocks”
section in the
Reconfiguration in
Stratix IV Devices
“Logical Channel
Addressing while
Reconfiguring the PMA
Controls” section in the
Dynamic Reconfiguration in
Stratix IV Devices
Reference
Table 1–8
Dynamic
chapter.
chapter.
lists
1–29
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