DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 741

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
User-Selected Receiver Phase Compensation FIFO Read Clock
The ALTGX MegaWizard Plug-In Manager provides an optional port named
rx_coreclk for each instantiated receiver channel. If you enable this port, the
Quartus II software does not automatically select the receiver phase compensation
FIFO read clock source. Instead, the signal that you drive on the rx_coreclk port of
the channel clocks the read side of its receiver phase compensation FIFO.
You can use the flexibility of selecting the receiver phase compensation FIFO read
clock to reduce the global, regional, or global and regional clock resource usage. You
can connect the rx_coreclk ports of all the receiver channels in your design and drive
them using a common clock driver that has a 0 PPM frequency difference with respect
to the FIFO write clocks of these channels. Use this common clock driver to latch the
receiver data and status signals in the FPGA fabric for these channels. This FPGA
fabric-Transceiver interface clocking scheme uses only one global, regional, or global
and regional clock resource for all channels.
Figure 2–37
serial data to all 16 channels has a 0 PPM frequency difference with respect to each
other. The rx_coreclk ports of all 16 channels are connected together and driven by a
common clock driver. This common clock driver also latches the receiver data and
status logic of all 16 receiver channels in the FPGA fabric. Only one global, regional, or
global and regional clock resource is used with this clocking scheme, compared to 16
global, regional, or global and regional clock resources needed without the
rx_coreclk ports (the Quartus II software-selected receiver phase compensation FIFO
read clock).
Example 8: Sixteen Identical Channels Across Four Transceiver Blocks
shows 16 channels located across four transceiver blocks. The incoming
Stratix IV Device Handbook Volume 2: Transceivers
2–69