DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 231

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–6. Number of DQS/DQ Groups per Bank in EP4SGX110 Devices with 16 Transceivers in the 1152-Pin FineLine
BGA Package
Notes to
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011 Altera Corporation
Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
of the ×4 group are used as R
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Figure
26 User I/Os
I/O Bank 1C
I/O Bank 1A
32 User I/Os
x16/x18=0
x16/x18=1
x8/x9=1
x8/x9=2
DLL0
DLL1
x4=3
7–6:
x4=4
(Note
1), (2), (3), (4),
I/O Bank 8A
40 User I/Os
I/O Bank 3A
40 User I/Os
x16/x18=1
x16/x18=1
UP
x8/x9=3
x8/x9=3
x4=6
x4=6
and R
DN
pins for OCT calibration. If two pins of a ×4 group are used as R
(5)
24 User I/Os
I/O Bank 8C
x16/x18=0
I/O Bank 3C
24 User I/Os
x8/x9=1
x16/x18=0
x4=2
x8/x9=1
in the 1152-Pin FineLine BGA
x4=2
EP4SGX110 Devices
(with 16 Transceivers)
7–26.
UP
24 User I/Os
I/O Bank 7C
x16/x18=0
24 User I/Os
I/O Bank 4C
x16/x18=0
x8/x9=1
and R
x8/x9=1
x4=3
x4=3
DN
pins, but you cannot use a ×4 group for memory interfaces if two pins
I/O Bank 7A
40 User I/Os
I/O Bank 4A
40 User I/Os
x16/x18=1
x16/x18=1
x8/x9=3
x8/x9=3
x4=6
x4=6
26 User I/Os
I/O Bank 6C
I/O Bank 6A
32 User I/Os
x16/x18=0
x16/x18=1
x8/x9=1
x8/x9=2
UP
x4=3
DLL3
x4=4
DLL2
Stratix IV Device Handbook Volume 1
and R
DN
“Combining ×16/×18 DQS/DQ
pins for OCT calibration, you
7–11