DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 142

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

5–26
Stratix IV Device Handbook Volume 1
PLL Control Signals
1
1
You can use the pfdena, areset, and locked signals to observe and control PLL
operation and resynchronization.
pfdena
Use the pfdena signal to maintain the most recent locked frequency so your system
has time to store its current settings before shutting down. The pfdena signal controls
the PFD output with a programmable gate. If you disable PFD, the VCO operates at
its most recent set value of control voltage and frequency, with some long-term drift to
a lower frequency. The PLL continues running even if it goes out-of-lock or the input
clock is disabled. You can use either your own control signal or the control signals
available from the clock switchover circuit (activeclock, clkbad[0], or clkbad[1]) to
control pfdena.
areset
The areset signal is the reset or resynchronization input for each PLL. The device
input pins or internal logic can drive these input signals. When areset is driven high,
the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The
VCO is then set back to its nominal setting. When areset is driven low again, the PLL
resynchronizes to its input as it re-locks.
You must assert the areset signal every time the PLL loses lock to guarantee the
correct phase relationship between the PLL input and output clocks. You can set up
the PLL to automatically reset (self reset) after a loss-of-lock condition using the
Quartus II MegaWizard™ Plug-In Manager. You must include the areset signal in
designs if either of the following conditions is true:
■
■
If the input clock to the PLL is not toggling or is unstable after power up, assert the
areset signal after the input clock is stable and within specifications.
locked
The locked signal output of the PLL indicates that the PLL has locked onto the
reference clock and the PLL clock outputs are operating at the desired phase and
frequency set in the Quartus II MegaWizard Plug-In Manager. The lock detection
circuit provides a signal to the core logic that gives an indication when the feedback
clock has locked onto the reference clock both in phase and frequency.
Altera recommends using the areset and locked signals in your designs to control
and observe the status of your PLL.
PLL reconfiguration or clock switchover is enabled in the design
Phase relationships between the PLL input and output clocks must be maintained
after a loss-of-lock condition
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
February 2011 Altera Corporation
PLLs in Stratix IV Devices