DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 545

• Manufacturer Part Number: DK-DEV-4SGX230N
• Description: KIT DEVELOPMENT STRATIX IV
• Manufacturer: Altera
• Series: Stratix® IVr
• Type: FPGAr

Specifications of DK-DEV-4SGX230N

• Contents: Development Board, Universal Power Supply, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GX
• Rohs Compliant: Yes
• For Use With/related Products: EP4SGX230K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2594

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–88. CMU0 Channel with the CMU0 PLL and CMU0 Clock Divider
Notes to
(1) To provide clocks for its PMA and PCS blocks in non-bonded functional modes (for example, GIGE functional mode), the transmitter channel uses
(2) Used in XAUI, Basic ×4, and PCIe ×4 functional modes. In PCIe ×8 functional mode, only the CMU0 channel of the master transceiver block provides
February 2011 Altera Corporation
the transmitter local clock divider to divide this high-speed clock output.
clock output to all eight transceiver channels configured in PCIe functional mode.
Figure
PLL Cascade Clock
Global Clock Line
Dedicated refclk0
Dedicated refclk1
ITB Clock Lines
pll_powerdown
pll_powerdown
1–88:
1
pll_locked
6
The following sections describe the CMU channel building blocks.
Configuring CMU Channels for Clock Generation
Each CMU channel has a CMU PLL that generates high-speed serial transceiver
clocks when the CMU channel is configured as a CMU. The CMU0 clock divider block
also generates the low-speed parallel transceiver clock for ×4, ×8, and ×N bonded
mode configurations such as XAUI, Basic ×4, Basic ×8, and Basic (PMA-Direct) ×N.
The CMU0 channel has additional capabilities to support bonded protocol functional
modes such as Basic ×4, XAUI, and PCIe. Use the ALTGX MegaWizard Plug-In
Manager to select these functional modes (to enable Basic ×4 functional mode, select
the ×4 option in Basic mode). For more information, refer to
page
For Stratix IV GT devices, you can use the CMU PLL to generate transceiver clocks at
data rates between 600 Mbps and 11.3 Gbps.
CMU0 Channel
The CMU0 channel, shown in
■
■
CMU0 PLL (refer to
CMU0 clock divider (refer to
1–110.
reference clock
CMU0 PLL
(to PCIe rate switch controller block in the CCU)
(to PCIe rate switch controller block in the CCU)
input
PCIE_gen2switch_done
PCIE_gen2switch
CMU0 PLL
“CMU0 Clock Divider” on page
Figure
“CMU Clock Divider” on page
High-Speed
High-Speed Clock
CMU0 PLL
Clock (1)
CMU1 PLL
1–88, contains the following blocks:
CMU0 Clock
Divider
CMU0 Channel
Stratix IV Device Handbook Volume 2: Transceivers
1–103)
High-Speed Serial Clock
for Bonded Modes (2)
Low-Speed Parallel Clock
for Bonded Modes
“Functional Modes” on
1–108)
1–101