DK-DEV-4SGX230N Altera, DK-DEV-4SGX230N Datasheet - Page 645
![KIT DEVELOPMENT STRATIX IV](/photos/28/41/284156/dk-dev-4sgx230n_sml.jpg)
DK-DEV-4SGX230N
Manufacturer Part Number
DK-DEV-4SGX230N
Description
KIT DEVELOPMENT STRATIX IV
Manufacturer
Altera
Series
Stratix® IVr
Type
FPGAr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.DK-DEV-4SGX230N.pdf
(2 pages)
4.DK-DEV-4SGX530N.pdf
(57 pages)
Specifications of DK-DEV-4SGX230N
Contents
Development Board, Universal Power Supply, Cables and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Stratix
Silicon Core Number
EP4S
Silicon Family Name
Stratix IV GX
Rohs Compliant
Yes
For Use With/related Products
EP4SGX230K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2594
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DK-DEV-4SGX230N
Manufacturer:
Altera
Quantity:
135
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- DK-DEV-4SGX230N PDF datasheet #3
- DK-DEV-4SGX530N PDF datasheet #4
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- Download datasheet (32Mb)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Calibration Blocks
Table 1–70. Differences Between the 10G ATX PLL, 6G ATX PLL, and CMU PLL (Part 2 of 2)
Calibration Blocks
February 2011 Altera Corporation
Power Supply—V
options for PLLs
Phase noise
Notes to
(1) Using the L dividers available in ATX PLLs.
(2) For improved jitter performance, Altera strongly recommends using the refclk pins of the transceiver block located immediately below the 10G
(3) For more information, refer to the Input Reference Clock Source table in the
(4) Option in Stratix IV GT devices.
(5) For more information about phase noise and PLL bandwidths of ATX and CMU PLLs, refer to the characterization reports.
Difference Category/PLLs
ATX PLL block to drive the input reference clock.
Table
Calibration Block Location
1–70:
CCA_L/R
Stratix IV GX and GT devices contain calibration circuits that calibrate the OCT
resistors and the analog portions of the transceiver blocks to ensure that the
functionality is independent of process, voltage, or temperature variations.
Figure 1–167
different Stratix IV GX and GT devices. In
calibration block R0 and L0 refer to the calibration blocks on the right and left side of
the devices, respectively.
Figure 1–167. Calibration Block Locations in Stratix IV GX and GT Device with Two Transceiver
Blocks (on Each Side)
(V)
Lower when compared
with the CMU PLL
10G ATX PLL
shows the location and number of calibration blocks available for
2K
3.3
Ω
ATX PLL L0
Calibration
(5)
Block L0
GXBL1
GXBL0
Lower when compared with the
Stratix IV GX and GT
Stratix IV Transceiver Clocking
CMU PLL
6G ATX PLL
Device
3.3
Figure 1–167
3.0 or
(4)
(5)
Stratix IV Device Handbook Volume 2: Transceivers
ATX PLL R0
Calibration
GXBR0
Block R0
GXBR1
through
chapter.
Higher when compared with
Figure
the ATX PLLs
2K
Ω
CMU PLL
3.3
2.5 or
3.0 or
1–172, the
(4)
(5)
1–201
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